The present invention relates to a semiconductor memory device with a so-called "redundancy function", i.e., preparing a redundant component to repair another equivalent one not functioning correctly due to a defect brought about during the manufacturing process of the device.
FIG. 10 illustrates a configuration of a conventional semiconductor memory device with a redundancy function (see Japanese Laid-Open Publication No. 6-139797). In FIG. 10, a memory array 101 includes a plurality of memory cells, each storing data thereon, and a redundant memory array 102 includes a plurality of redundant memory cells to repair defective components possibly included in the memory array 101.
The semiconductor memory device shown in FIG. 10 operates in the following manner. When the device is externally accessed, an address input circuit 103 outputs an address signal associated with an address specified. A decoder 104 decodes the address signal and outputs the decoded signal to a data bus switching circuit 109. At the same time, a redundant driver 105 also generates a signal and provides the signal to the data bus switching circuit 109. Responsive to the decoded signal, the data bus switching circuit 109 electricaly connects a data line IO to a particular memory cell associated with the specified address in the memory array 101. Also, responsive to the output signal of the redundant driver 105, the switching circuit 109 electrically connects a redundant data line RIO to the redundant memory array 102.
The addresses of defective memory cells are stored in advance in a redundancy decision circuit 106. Responsive to the address signal, the redundancy decision circuit 106 compares the address specified to those of the defective memory cells. If one of those addresses matches up to the address specified, then the redundancy decision circuit 106 gets the data read out by a data readout amplifier 108 from the redundant memory array 102 and then output by a data output circuit 110. Alternatively, if none of the addresses match up to the address specified, then the redundancy decision circuit 106 gets the data read out by another data readout amplifier 107 from the memory array 101 and then output by the data output circuit 110.
In this manner, an externally input address is compared to the pre-stored addresses of defective memory cells, and if the input address matches up to one of those addresses, an equivalent memory cell included in the redundant memory array is accessed to repair the defective memory cell. As a result, the yield of the semiconductor memory device is improved.
In recent years, to improve the data transfer capability of a semiconductor memory device, multi-bit accessing, which makes a multiplicity of memory cells accessible with just one address specified, has been implemented.
If a semiconductor memory device with the conventional redundancy function as shown in FIG. 10 is accessed by multi-bit accessing, however, the efficiency of repair is poor. For example, suppose just one defective memory cell is included in 128 memory cells corresponding to a single address specified for a 128-bit semiconductor memory device. In such a case, if the address is pre-stored in the redundancy decision circuit to repair the defective memory cell with a redundant one, then not only the single defective memory cell, but also the other normal 127 memory cells are replaced with respective redundant memory cells. In other words, to repair the single defective memory cell, the 127 normal memory cells are all disabled. Thus, such a repair method is far from being efficient.